1. Field of the Invention
The present invention relates to non-volatile-memory based programmable logic devices. More particularly, the present invention pertains to memory cells for use in non-volatile-memory based programmable logic devices such as field-programmable-gate-array (FPGA) devices.
2. The Prior Art
Numerous non-volatile memory cells have been proposed for use in programmable logic devices such as FPGAs. As non-exhaustive examples, U.S. Pat. No. 6,144,580 discloses embodiments where p-channel and n-channel non-volatile MOS transistors are connected in series and have different control gate connection arrangements. U.S. Pat. No. 6,356,478 discloses p-channel and n-channel non-volatile MOS transistors sharing a common floating gate and a common control gate. U.S. Pat. No. 5,740,106 discloses several different variations on p-channel and n-channel non-volatile MOS transistors connected in series. Some share common floating gates. U.S. Pat. No. 5,847,993 discloses several different variations on p-channel and n-channel volatile and non-volatile MOS transistors connected in series. Some share common floating gates. U.S. Pat. No. 5,640,344 discloses p-channel and n-channel non-volatile MOS transistors sharing a common floating gate and a common control gate.
In addition, as geometries shrink for user-programmable devices such as FPGAs, so do the maximum voltages that the transistors used to build these devices can withstand. This presents a problem in that the voltages used to program and erase non-volatile memory transistors are not decreasing as fast as the voltages that are used to operate the transistors from which the logic is configured. In order to take advantage of the ever decreasing logic-transistor geometries, the logic circuitry needs to be protected from the programming and erase potentials that are encountered in the FPGA programming circuitry.